1. Field of the Invention
The present invention generally to a shield circuit for shielding a wire and an integrated circuit in which the shield circuit is used to shield at least a portion of the wires.
2. Description of the Related Art
FIG. 6 is a circuit diagram showing a shield circuit according to the related art. Referring to FIG. 6, reference numeral 101 indicates a wire subject to shielding, 102 indicates a cell for driving the wire 101 based on values at inputs 104 and 105, 103 indicates a cell connected to the cell 102 via the wire 101, and 106 and 107 indicate shielding wires that are grounded to provide shielding.
A description will now be given of the operation according to the related art.
The shielding wires 106 and 107 are grounded so that the wire 101 is shielded from other wires (not shown).
With this shielding of the wire 101, noise such as cross talk is suppressed and the magnitude of inductance with respect to other wires is reduced.
The shielding according to the related art, however, has a drawback in that capacitance between the shielding wires 106, 107 and the wire 101 is increased so that the delay of a signal traveling in the wire 101 is increased.
One approach to reduce the delay in signal propagation is ensure that the potential of the shielding wire is identical with the target wire subject to shielding. FIG. 7 is a circuit diagram of another related-art shield circuit disclosed in Japanese Laid-Open Patent Application No. 8-306867. Referring to FIG. 7, reference numeral 121 indicates a wire subject to shielding, 131 indicates a cell that drives the wire 121, 122L and 122R indicate shielding wires provided to sandwich the wire 121 and in the same layer as the wire 121. Numeral 123 indicates a shielding wire provided in another layer and 132 indicates a cell of the same type as the cell 131, for driving the shielding wires 122L, 122R and 123.
A description will be given of the operation according to the alternative related art.
Signals propagated through the wire 121, the shielding wires 122L, 122R and 123 maintain the same phase. Even if the wire 121, and the shielding wires 122L, 122R and 123 are coupled by stray capacitance, no charging or discharging occurs as a result of the capacitance because of this same phase feature.
It is thus ensured that the target wire 121 is shielded and the delay in signal propagation caused by the capacitance between wires is reduced.
Since the alternative related art is constructed such that the cell 132 of the same cell type as the cell 131 that drives the target wire 121 is used to drive the shielding wires 122L, 122R and 123, it is difficult to reduce the scale of the shield circuit while reducing a delay in the signal propagation.
Accordingly, a general object of the present invention is to provide a shield circuit and an integrated circuit having the same, in which the aforementioned problem is eliminated.
Another and more specific object is to provide a shield circuit with a reduced circuit scale and an integrated circuit having the same, in which the delay in signal propagation is reduced by providing shielding wires along a target wire that requires shielding, and providing a shielding wire driving circuit that drives the shielding wires with a logical value corresponding to a logical value of at least one of inputs to the cell that drives the target wire.
The aforementioned objects can be achieved by a shield circuit for shielding a target wire that requires shielding, comprising: shielding wires provided along a target wire that requires shielding; and a shielding wire driving circuit for driving the shielding wires with a logical value corresponding to a logical value of at least one of inputs to a cell that drives the target wire.
The shielding wire driving circuit may comprise one of an inverter and a buffer.
The shielding wires may include a first shielding wire and a second shielding wire, and the shielding wire driving circuit may include a first circuit for driving the first shielding wire and a second circuit for driving the second shielding wire.
At least one of the shielding wires may be divided along the target wire to produce individual shielding wires.
The shielding wire driving circuit may drive the shielding wires using a cell having a lower driving capability than the cell that drives the target wire.
The aforementioned objects can be achieved by an integrated circuit in which a target wire that requires reduction in delay in signal propagation is shielded, comprising: a shield circuit for shielding the target wire, wherein the shield circuit is provided with shielding wires provided along the target wire and with a shielding wire driving circuit for driving the shielding wires with a logical value corresponding to a logical value of at least one of inputs to a cell that drives the target wire.